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Application Report

SLAA154 – October 2002

Interfacing the TLV320AIC12/13/14/15 Codec to the

TMS320C5402™ DSP

Bolanle Onodipe High Performance Analog Products

ABSTRACT

This application report presents the process of interfacing of the TLV320AIC12/13/14/15

voice-band codec with the TMS320C5402™ DSP. It presents the hardware configuration

and the software driver for a two-device cascade (single master and single slave)

configuration mode. The design can be considered as an application example, a test tool,

or a startup platform for developing and using the codec/DSP system.

Contents

1 Introduction...................................................................................................................................2

2 Hardware System..........................................................................................................................3

2.1 Basic Stand-Alone Master Codec/DSP Interface.....................................................................3

2.2 Basic Two-AIC12 Cascade Codec/DSP Interface ...................................................................4

2.3 Codec/C5402™ DSP Starter Kit System.................................................................................4

3 Software Interface.........................................................................................................................4

3.1 Codec Control Register Initialization .......................................................................................4

3.2 Analog Interface......................................................................................................................6

3.2.1 Analog Inputs ..............................................................................................................6

3.2.2 Analog Outputs............................................................................................................6

3.3 Digital Interface.......................................................................................................................6

3.4 Interface Data Format .............................................................................................................7

3.5 Control Frame Data Format ....................................................................................................9

4 Design Issues..............................................................................................................................10

5 Test Procedure for AIC12...........................................................................................................11

5.1 TLV320AIC Development Platform Board Setup...................................................................11

5.2 SYNC RESET Synchronization Test .......................................................................................11

5.3 AIC12 EVM Board.................................................................................................................12

5.4 AC Test.................................................................................................................................13

6 References ..................................................................................................................................13

Figures

Figure 1. Typical AIC12/C54xx™ DSP Digital Interface, Stand-Alone Master Operation...................3

Figure 2. Typical AIC12/C54xx™ DSP Digital Interface, Two-AIC12 Cascade Mode ........................5

Figure 3. Master / Slave Communication in Programming Mode.......................................................7

Figure 4. Master / Slave Communication in Continuous Mode ..........................................................8

Figure 5. Data Frame Format............................................................................................................8

Figure 6. Control Frame Data Format................................................................................................9

TMS320C5402, TMS320C54xx, TMS320C28xx, and TMS320C6xxx are trademarks of Texas Instruments. All trademarks are

the property of their respective owners.

1 2 3 4 5 6 ... 14 15

Inhaltsverzeichnis

Seite 1 - TMS320C5402™ DSP

Application ReportSLAA154 – October 20021Interfacing the TLV320AIC12/13/14/15 Codec to theTMS320C5402™ DSPBolanle Onodipe High Performance Analog Prod

Seite 2 - 1 Introduction

SLAA15410 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSPTable 1. Control Register Address ChartRegister Address D15 D14 D13 Regist

Seite 3 - 2HardwareSystem

SLAA154Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP 115 Test Procedure for AIC12.5.1 TLV320AIC Development Platform Board Setup1

Seite 4 - 3 Software Interface

SLAA15412 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSPWith the scope in the single trigger mode, and set the scope sync to trigg

Seite 5 - SMARTDM Port

SLAA154Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP 135.4 AC TestWith the jumper settings as described above, apply a periodic s

Seite 6 - 3.3 Digital Interface

SLAA15414 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP[11] TMS320C54x DSP Mnemonic Instruction Set, Reference Set Volume 2 (SPRU

Seite 7

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvemen

Seite 8 - D15 through D0

SLAA1542 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSPTablesTable 1. Control Register Address Chart...

Seite 9 - D15-D12 D11-D9 0 D7-D0

SLAA154Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP 3An AIC12 device is defined a master or a slave on the basis of the origin o

Seite 10 - 4 Design Issues

SLAA1544 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSPIn the Figure 1, note that the reset and power-down signals must be synchro

Seite 11 - 5 Test Procedure for AIC12

SLAA154Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP 5'C54xxDSPMcBSPBCLKRBCLKXBFSRBFSXBDRBDXCLKOUT'AIC12#0DINDOUTFSSCLK

Seite 12 - 5.3 AIC12 EVM Board

SLAA1546 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP3.2 Analog InterfaceThe AIC12 device has a full complement of analog input

Seite 13 - 6 References

SLAA154Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP 7The following equations determine the respective frequencies:• FS (frame s

Seite 14

SLAA1548 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSPWithin each frame, the data frame for each device is transmitted first in o

Seite 15

SLAA154Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP 93.5 Control Frame Data FormatThe codec’s control frame data is composed of

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AMX Codec Master Control System Spezifikationen