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UG197 (v1.5) July 22, 2009

Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions

CRMDOHOTRESETN

Output core_clk Hot reset (active Low). Asserted on completion of hot reset

handshake as a prompt for user logic to be reset. See “Resets,”

page 23.

CRMPWRSOFTRESETN

Output core_clk Soft reset (active Low). Asserted when the block makes the

transition from D3

hot

to D0

uninitialized

, as a prompt for user logic

to be reset (with

CRMUSERCFGRSTN).

Table 2-3: Clock and Reset Ports (Continued)

Port Direction

Clock

Domain

Description

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 ... 119 120

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