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Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 69

UG197 (v1.5) July 22, 2009

Interrupt Handling

Disable bit in the PCI Command register is set to 0. This is reflected on the

INTERRUPTDISABLE output:

•

INTERRUPTDISABLE = 0: interrupts enabled

•

INTERRUPTDISABLE = 1: interrupts disabled (requests are blocked)

The MSI Enable bits in the MSI Control register and the Interrupt Disable bit in the PCI

Command register are programmed by the Root Complex. The user application has no

direct control over these bits.

Interrupts are generated using the Endpoint Block Plus wrapper’s configuration and

interrupt interface. The Endpoint Block Plus wrapper contains logic that polls the

integrated Endpoint block’s management interface to read the MSI Enable bit. The

wrapper provides a signal output to the user informing what type of interrupt is being

used. See the LogiCORE Endpoint Block Plus Wrapper User Guide for more information.

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AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE Betriebsanweisung Seite 69